The present invention relates to digital microprocessors, and more particularly to multiplier and multiplier/accumulator circuits for digital microprocessors.
Microprocessors are general purpose processors which require high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications.
DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Typically, a DSP includes a multiply-accumulate (MAC) that performs computations using coefficients fetched from memory or stored in registers.
Particularly in, but not exclusively, applications such as mobile telecommunications applications, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a microprocessor that is a programmable digital signal processor (DSP), offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The microprocessor has a stand alone coefficient data pointer and circuitry for tracking coefficient data pointer modification sequences, such that coefficient fetches from memory are minimized in either a single MAC embodiment or in a dual MAC embodiment, whereby power consumption is reduced.
In accordance with another aspect of the present invention, there is a shadow register to hold coefficient data. Redundant memory accesses for a reused coefficient data value are eliminated, thereby preserving memory bandwidth and eliminating memory conflicts and thereby improving processing speed.
In accordance with another aspect of the present invention, a touch instruction xe2x80x9cmar(*CDP)xe2x80x9d is provided to flag that a coefficient has been updated from a memory write so that the updated coefficient can be fetched for use by the MAC.
In accordance with another aspect of the present invention, an override mechanism is provided to disable the power saving scheme for debug purposes.
In accordance with another aspect of the present invention, coefficient data pointer modification tracking circuitry is simplified by only tracking pointer modification during looping operations.
In accordance with another aspect of the present invention, a method of operating a digital system comprising a microprocessor is provided that includes the steps of: loading a data pointer with an address value; executing a first instruction that requires at least an operand from memory in accordance with the data pointer by fetching the operand from memory in accordance with the address value; and repeating the first instruction or executing a second instruction that requires at least an operand from memory in accordance with the data pointer by inhibiting refetching of the operand from memory if the data pointer has not been modified since the step of executing the first instruction.